The present invention relates to isolation structures in semiconductor device. More particularly, the invention relates to indium implants in shallow trench isolation structures to improve punchthrough protection in semiconductor devices.
As transistor active areas and isolation structures shrink, field isolation structures also need to be miniaturized. To isolate the active transistor areas different isolation techniques are employed to avoid electrical current and malfunctioning of the device. The most important isolation techniques are LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation). For deep-submicron technologies STI is more favorable because of less space consumption due to less lateral encroachment. This allows an increase in integration density and decrease in device spacing. However, not only the isolation structure itself has to be minimized, also the wells where the devices will be placed have to be adapted with regard to field-punchthrough and latch-up immunity.
A conventional shallow trench isolation typically involves depositing an oxide layer on the surface of a semiconductor substrate, followed by deposition or formation of a nitride layer that is patterned to act as a mask for shallow trench etch. The nitride mask also has a role as a proper in-situ control layer for CMP, and preventing further oxidation of the substrate surface where it is masked. The next step involves etching of the shallow trench followed by formation of an oxide liner in the shallow trench. Following formation of the oxide liner, the trench is filled with deposited oxide, and the partly formed device is subjected to CMP to planarize down to the top of the trench and to the substrate layer adjacent to the trench. Next, the p- and n-wells are implanted using n-well and p-well masks on the corresponding sides.
The most commonly used dopant species for p- and n-wells are boron and phosphorus, respectively. The p-well and n-well dopings form a p-n junction under the field oxide of adjacent n+ and p+ diffusion regions. It is important for the device operation that these two diffusion regions (devices) are clearly electrically separated. However, boron tends to diffuse out from the p-well into the substrate, towards the shallow trench and segregate into its oxide. This situation is illustrated in FIG. 1 which depicts a plot 100 of the dopant profile in a cross-section of the silicon substrate underneath the field isolation and in the field isolation above the substrate for a typical CMOS device. Curve 102 represents the doping conditions within a typical p-well underneath the isolation, whereas curve 106 represents a typical n-well doping underneath the isolation displayed as vertical cross-section in a non-compensated well scheme. Both curves 102 and 106 represent the doping conditions in a compensated n-well. As boron 102 tends to deplete at the field isolation/silicon interface 104, phosphorus 106 tends to pile-up. Therefore the p-doping is weaker under the oxide and prone to field-punchthrough in a p-well region.
In older technologies, it was possible to perform a boron field implant prior to field oxidation to strengthen the p-doping directly under the field oxide. However, due to decreasing device and isolation dimensions, such boron doping would diffuse and contribute to the narrow-width channel doping and increase the threshold voltage for narrow-width n-channel devices.
Thus, what is needed is a technique for achieving better field-punchthrough protection in STI devices.
To achieve the foregoing, the present invention provides a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is about an order of magnitude smaller than that of boron and the activation level of indium is high enough for well doping levels. Thus, the implanted indium is able to keep the concentration of p-dopant at the lateral p-n well junction and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.
In one aspect, the invention provides a process for forming a shallow trench isolation in a semiconductor device. The process involves depositing a pad oxide layer on the surface of a silicon substrate, forming a shallow trench in the substrate, forming an oxide liner in the shallow trench thereby creating a silicon/oxide interface in the trench, implanting indium into the trench, and filling the trench with oxide.
In another aspect, the invention provides a semiconductor device. The device includes a pad oxide layer on the surface of a silicon substrate, a shallow trench in the substrate separating two or more device regions, the trench having sidewalls and a bottom, oxide filling the trench and forming a shallow trench isolation having an interface with the silicon substrate, and an indium implant region adjacent to the bottom of the shallow trench isolation.
These and other features and advantages of the present invention are described below with reference to the drawings.